1. Field of the Invention
The present invention relates to a data processing apparatus and a data processing method.
2. Description of the Related Art
Conventionally, when data is read from a memory card such as an SD card, the delay amount of data transmission from the card relative to a clock given by a host to the card has been a standardized fixed value. A host side can therefore receive data from the card successfully and access the card without any problems by latching the data transmitted from the card at a timing delayed relative to the clock transmitted from the card by a predetermined amount.
Recently, however, the aforementioned delay amount cannot be defined by the fixed value because the speed of the clock for data transmission/reception between the memory card and the host increases along with an increase in the access speed of the memory card. For this reason, UHS-1 (Ultra High Speed-1) as the high-speed standard of the SD memory card defines that a data latch timing adjustment is necessary when using a clock of a predetermined frequency. This latch timing adjustment operation is referred to as tuning (see Japanese Patent Laid-Open No. 2011-134009).
However, the delay amount of the clock for latching data varies according to external factors such as a card temperature. Therefore, if card access is repeated for many hours, for example, when writing data in the card successively, the delay amount changes along with a change in the card temperature, resulting in a failure in data read/write. In this case, it is considered to perform tuning processing again. However, since data cannot be read/written from/in the card while tuning, tuning more than necessary leads to a decrease in a transfer rate.